1. Field of the invention
The present invention relates to improvement of receivers which are intermittently operated for saving a power consumption of an associated electric battery and, more specifically to such intermittent receivers constituted of a small amount of circuit elements.
2. Description of Related Art
Heretofore, a so-called intermittent receiver is composed of a time signal generator 10 and a delayed detector 12, as shown in FIG. 1. The time generator 10 has a shift register 14 formed of a plurality of cascaded D-type flipflops 16A to 16N, which have respective clock inputs C commonly connected to receive a clock C.sub.T. A Q output of the last flipflop 16N and a Q output of the penultimated flipflop 16M are connected to an exclusive-OR gate 18, whose output is connected to a data input D of the first flipflop 16A. Each of the flipflops 16A to 16M excluding the final flipflop 16N are connected at their Q outputs to corresponding inputs of a plurality of NOR gates 20 arranged in parallel to each other. A Q output of the final flipflop 16N is also connected to one input of one of the NOR gates 20. Outputs of all the NOR gates 20 are connected to inputs of the NAND gate 22, which, in turn, generates an output time pulse V.sub.T. Thus, the NOR gates 20 and the NAND gate 22 constitute together a decoder 24 for detecting a predetermined condition of the shift register 14, and therefore, the shift register 14 and the decoder 24 form a frequency divider for frequency-dividing the clock signal C.sub.T by a divisor determined by the number of the flipflops.
The time pulse V.sub.T generated by the time signal generator 10 is supplied to a controller 26, which generates a switching signal V.sub.S for selection between a wait or rest mode and a reception mode. This switching signal V.sub.S is inputted to a power switch circuit 30, which operates to selectively supply an electric power to either the time signal generator 10 or the delayed detector 12.
The delayed detector 12 includes a shift register 32 composed of a plurality of cascaded D-type flipflops 34A to 34S which commonly receive a clock C.sub.S at their respective clock input C. A data input D of the first flipflop 34A constitutes an input of the delayed detector 12 and is connected to receive a reception signal V.sub.R. The reception signal V.sub.R and the delayed signal V.sub.D outputted from a Q output of the final flipflop 34S are supplied to a pair of inputs of an exclusive-OR gate 36, whose output generates a detection signal V.sub.O as an output of the delayed detector 12.
With the above arrangement, an electric power is intermittently supplied to the delayed detector 12 for a short continuous time period in the order of several ten milliseconds at constant intervals of several ten seconds to several minutes. For the other times, the electric power is supplied to the time signal generator 10.
Referring to FIG. 2, there is illustrated one example of the switch signal V.sub.S generated by the controller 26. The shown switch signal V.sub.S is a pulse signal having a high level period of T.sub.1 which corresponding to the intermittent operation period of the delayed detector 12, namely, the period of the reception mode of the intermittent receiver. In this reception mode, the electric power is supplied to the delayed detector 12 so that the inputted reception signal V.sub.R is delayed and detected by the delayed detector 12. The length of this reception mode is determined by the controller 26. On the other hand, a low level period T.sub.2 of the switch signal V.sub.S corresponds to the wait mode in which the electric power is supplied to the time signal generator 10 but not supplied to the delayed detector 12. The length of this low level period T.sub.2 is determined by the frequency of the clock C.sub.T and the frequency division ratio determined by cooperation of the shift register 14 and the decoder 24.
More specifically, as shown in FIG. 3, the reception signal V.sub.R is composed of a Minimum Shift Keying signal having such a ratio of frequency that on an assumption that the frequency of a signal portion representative of one bit data of the logic value "1" is 1, the frequency of a signal portion representative of one bit data of the logic value "0" will be 1.5, and the signal portion representative of one bit data of the logic value "1" has a length of one wavelength and the signal portion representative of one bit data of the logic value "0" has a length of one and half wavelength, so that the signal portion representative of one bit data of the logic value "1" and the signal portion representative of one bit data of the logic value "0" have the same length of time. Such a reception signal V.sub.R is obtained by shaping a signal RF transmitted in the form of a radio wave into a pulse signal form, and then inputted to the delayed detector 12. The inputted signal V.sub.T is branched to the shift register 34 and the exclusive-OR gate 36. The signal V.sub.R inputted to the shift register 34 is delayed by the time period corresponding to one bit, and then, is outputted as the delayed signal V.sub.D as shown in FIG. 4 to the input of the exclusive-OR gate 36. Thus, an exclusive-OR between the signals V.sub.R and V.sub.D is effected in the gate 36 and the result of the logical operation is outputted as a detection signal V.sub.O.
Thereafter, the detection signal V.sub.O is passed through a lowpass filter (not shown) so that it is converted into a signal V.sub.F, which is in turn further shaped to a digital signal DT by means of an appropriate means (not shown).
As will be apparent from the above mentioned description, the conventional intermittent receiver is such that a time signal generator and a delayed detector have independent shift registers, respectively, although these shift registers are alternatively caused to operate. In other words, when one of the two shift registers is in operation, the other shift register is in a non-operation condition. Therefore, the circuit construction is very redundant, and the use efficiency of the circuit elements is low. This would be a one obstacle to integration of the intermittent receiver.